Introduction to VLSI design and testing course
Introduction to MOS transistors-Types of MOSFET-
Working of MOS transistor- Enhancement and depletion mode transistor
Different modes of operation of MOSFET-DC bias equation-Threshold voltage equations
Second order effects-Body effect- channel length modulation-Drain puch through, Hot carrier effect
Static CMOS logic-CMOS inverter- working
NAND,NOR implementation-Implementation of boolean function
Switch logic- MOS switches-properties of pass transstor and TG-Implementation
Transparent latch- Edge triggered register-master slave D FF using transmission gate
current voltage relationship of MOSFET-MOS Capacitor
CMOS logic circuits- Implementation of decoders and function realization
Ratioed logic-psuedo nmos logic-Psuedo nmos inverter
DC transfer characterisitics of CMOS inverter
DC characteristics- Noise margin- Introduction to dynamic logic
Dynamic logic- working- properties- problems in dynamic logic
Monotonicity in dynamic logic-Noise problem- Domino logic-Domino cascade
clocked CMOS logic- Design problems
Problems in body effect- Discussion on threshold voltage, current calculations
Integrated circuits- steps involved in IC fabrication- Si wafer processing
CZ crystal growth process- Nmos Fabrication
CMOS Fabrication process- n well CMOS process
P- well fabrication process- Twin tub process
Silicon on insulator process- Advantages and drawbacks
Ga As technology- compparison of cmos, bipolar, GaAs Technologies
Ga As fabrication-MESFET- steps involved in fabrication
Basic circuit concepts- sheet resistance- calculations-Area capacitance
Area capacitance-problems- calculation of Zpu/ Zpd ratio for nMOS inverter
Inverter delays- wiring capacitances- Diffusion, peripheral, side wall capacitance
Calculation of inverter delays- problems-cascaded inverters as buffer
Scaling- scaling laws- scaling models and scaling factors in combined V and D model
Latch up problem in bulk CMOS-Prevention techniques
CMOS inverter delay- Rise time and fall time estimation
sub system design process-Design rules- Basics- stick diagram
stick diagram-NAND,NOR gate- steps involved- standard cell design
Drawing stick diagram and symbolic diagram- TG - 2:1 and 4:1 MUX
BiCMOS inverter- stick and symbolic diagram-Euler path method
Design rules- Lambda based and Micron Rules-Designrules for Nmos and CMOS
Rules-Active,diffusion, polysilicon,contact cuts-Buried and Butting contacts-
sub system process- General considerations-
semiconductor memories- RAM organization-SRAM,DRAM-1T and 3T DRAM cell-Readand write operation
static RAM- 4T and 6T SRAM cell- Read and write operation
VLSI Testing aspects-Fault- stuck at fault- stuck open fault-Bridging fault
Testing combinational circuit- path sensitzation approach-principle
Path sensitization approach- Examples- Drawbacks- Need of D lagorithm
Path sensitization method- problems- Boolean difference
D- algorithm- singular cover, propagation D cube, primtive D cube, D intersection
steps involved in D- algorithm- Examples-Deriving test vector-PODEM algorithm
Design of testable sequential circuits
Scan design techniques-scan path approach- Boundary scan-BIST and objectives-BILBO
Scan design techniques-scan path approach-controllability and observability- Adhoc rules
Revision
Revision unit-II
Revision-Testing algorithms
